Substrates with interlayer connections between the two main surfaces are needed for the vertical integration of semiconductor circuits. Stacks are formed from such substrates, and in this way complex three-dimensional circuits are built from the integrated electronic components in the individual substrates. The production of long interlayer connections with small diameters requires long etching times, which make the production process expensive. Therefore, the semiconductor bodies are thinned to typical thicknesses of 200 μm to 300 μm before the production of the interlayer connections. Typical aspect ratios, that is, quotients of the length and the diameter of an interlayer connection, are 5:1 or 10:1. In the case of a substrate thickness of, for example, 250 μm, the diameters of the interlayer connections are typically limited to 25 μm to 50 μm. Aspect ratios of more than 50:1 currently lie outside of technical capabilities.
Substrates with interlayer connections and associated production methods are described in U.S. Pat. Nos. 6,461,956 B1, 7,030,466 B1, 5,122,856, and 7,179,740 B1. The method described in U.S. Pat. No. 6,461,956 B1 starts with an SOI (silicone-on-silicone) substrate, in which an insulation layer is arranged between silicon layers. One silicon layer, typically designated as the body silicon layer, is used for the integration of electronic components. The thicker silicon layer, which is typically designated as the bulk silicon layer and which is present on the opposite side of the insulation layer, has an opening, which is filled with a metal connected through an opening in the insulation layer to vertical interlayer connections of the body silicon layer and wiring arranged on this layer. In this way, a vertical electrically conductive connection is formed between a reverse-side terminal and a metallization layer of the top-side wiring.